This application relies for priority upon Korean Patent Application No. 2000-066543, filed on Nov. 9, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention generally relates to semiconductor memory devices and, more specifically, to a semiconductor memory device capable of read out normally data with a low power supply voltage.
FIG. 1 is a block diagram showing a data output construction in semiconductor memory device according to the conventional art.
Referring to FIG. 1, a plurality of registers R0xcx9cRn correspond to a single data line DL, and respectively store data bits read from a data storage region or a memory cell array. The registers R0xcx9cRn are connected to the data line DL through corresponding selection transistors M0xcx9cMn which are respectively controlled by corresponding selection signals SEL0xcx9cSELn. Here, the selection signals SEL0xcx9cSELn are sequentially activated in accordance with decoded results of address.
An inverter I11 is connected to the data line DL. Inverter I11 serves as a driver for transferring the data of the data line DL to an output terminal.
In a circuit operation, it is assumed that one, e.g., SEL1, of the selection signals SEL0xcx9cSELn is selected. Selections is by controlling the voltages. The selected signal SEL1 has power supply voltage Vdd, while the other signals SEL0 and SEL2xcx9cSELn have ground voltage. Thus, the N-channel metal oxide semiconductor (NMOS) transistor M1 is turned on, while the NMOS transistors M0, and M2xcx9cMn are turned off. Accordingly, a data bit held in the register R1 is transferred to the data line DL through the turned-on NMOS transistor M1.
Transfer is as follows: If the data bit held in the register R1 is xe2x80x9c0xe2x80x9d, the inverter I11 provides data bit DOUT of xe2x80x9c1xe2x80x9d by responding to a discharged potential of the data line DL. If the stored data bit in the register R1 is xe2x80x9c1xe2x80x9d, the potential of the data line DL is Vddxe2x88x92Vth. Vth is a threshold voltage of the NMOS transistor. The difference is because the power supply voltage corresponding to the data bit xe2x80x9c1xe2x80x9d is dropped by an amount equaling the threshold voltage Vth of the NMOS transistor M1.
A problem in the prior art arises at high speeds. In the circuit of FIG. 1, when the next decoding output is activated fast, it will be before the prior output has become inactive. This means that the activation periods of two successive selection signals overlap.
As a result of overlapping, output terminals of the registers corresponding to the signals become connected to each other, resulting in losing the data bits stored in the registers. And then, if the stored data bit is xe2x80x9c1xe2x80x9d, the potential of the data line DL becomes Vddxe2x88x92Vth, for the reason described above. In the case that the potential of the data line DL is lower than a trigger voltage of the inverter I11 by the lowered power supply voltage Vdd, the data cannot read out normally.
It is, therefore, an object of the present invention to provide a semiconductor memory device capable of normally reading out data even at a low power supply voltage level.
It is another object of the present invention to provide a semiconductor memory device capable of preventing data register selection signals from overlapping.
In order to attain the above objects, according to an aspect of the present invention, there is provided a semiconductor memory device having at least one data line, a plurality of registers for storing data bits, a plurality of switch elements for transferring the stored data bits to the data line. The device includes a precharge circuit connected to the data line, for precharging the data line to a power supply voltage.
According to the semiconductor memory device of the present invention, the data can be read out even in low power supply voltage by precharging the data line to the power supply voltage.
Additional features and advantages of the invention will be understood from the following description and drawings, in which: